The present invention relates to the speed-up of differential data transmission in a semiconductor integrated circuit.
For the realization of high-speed semiconductor integrated circuits, demand for high-speed differential data transmission has been growing increasingly in recent years.
In a synchronous DRAM that is one of the MOS semiconductor memory devices, both a continuous data read operation in synchronization with an externally-applied clock signal and a continuous data write operation in synchronization with the clock signal are required. U.S. Pat. No. 5,546,346 discloses a fast, low-power differential transmission circuit for synchronous DRAMs. This differential transmission circuit is described. A data read amplifier for differentially amplifying data read onto a pair of complementary signal lines (DQ line pair) from a memory cell for forwarding onto another pair of complementally signal lines (DB line pair) is formed by N&PMOS cross-coupled amplifiers. Pipelining processing is employed in which one differential data transmission cycle comprises four periods. The first period is a stage for individually and simultaneously voltage-equalizing the DQ line pair and the DB line pair. The second period is a stage for receiving data onto the DQ line pair while continuously voltage-equalizing the DB line pair. The third period is a stage for establishing communication between the DQ line pair and the DB line pair for transmitting the data on the DQ line pair onto the DB line pair. The fourth period (i.e., the last period) is a stage for disconnecting the DQ-DB communication to voltage-equalize the DQ line pair while holding the data on the DB line pair.
The above-described differential transmission circuit is problematic in some case. If there occurs a shift from the second period to the third period when a voltage swing occurring on the DQ line pair is small therefore starting the sensing operation onto the DB line pair, this results in the occurrence of error data on the DB line pair due to the malfunction of the N&PMOS crossed-coupled amplifiers. In order to avoid such an unwanted event, the following is required. That is, a control clock signal for controlling the foregoing pipelining processing must be generated from a clock signal provided from outside the synchronous DRAM so that it is not until the moment there is produced a potential difference of not less than a certain amount between the DQ line pair (i.e., a target potential difference necessary for normal operations) that the sensing operation onto the DB line pair starts. The problem is that it is extremely difficult to control the timing of generation of a control clock signal so that the sensing operation onto the DB line pair timely starts when the potential difference between the DQ line pair reaches a target amount. When making an attempt that every operation is carried out normally, it is required to allow a time margin for generation of the control clock signal so that the control clock signal generation is somewhat delayed with respect to the lowest possible timing. This produces the problem that high-speed data transmission beyond a certain limit cannot be realized.